Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a bit into the SRAM cell or read from the SRAM cell.
With the scaling of integrated circuits, the operation voltages of integrated circuits are reduced, along with the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which measure how reliably the bits of the SRAM cells can be read from and written into, respectively, are reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations.
FIG. 1 illustrates a portion of a conventional SRAM array, which includes a plurality of SRAM cells cell1 through celln in a same column. Power supply line 12 supplies power to SRAM cells cell1 through celln. SRAM cell cell1 is close to the starting point of the power supply line 12, which starting point is where the power supply line 12 receives power supply voltage VDD. SRAM cell celln is close to the end point of the power supply line 12, at which the power supply line 12 terminates. In very small-scale integrated circuits, the power supply line 12 becomes very thin and narrow, and hence its resistance is no longer negligible. The power supply voltage provided to point 14 will thus be noticeably lower than supply voltage VDD due to the voltage drop on power supply line 12.
Conventionally, to improve the read and write margins, dynamic powers are provided, which means different power supply voltages VDD are provided for read and write operations. For example, the write margin can be improved by reducing the power supply voltage VDD during the write operations, while the read margin can be improved by increasing the power supply voltage VDD during the read operations. However, such a solution suffers from drawbacks when used in very small-scale integrated circuits. For example, when SRAM cell celln is being written into, it drains current from, and hence causes instantaneous voltage drop on, power supply line 12. This is beneficial to the write operation as the write margin is improved. However, SRAM cell celln-1 is close to SRAM cell celln, and hence suffers from similar instantaneous voltage drop. Since the power supply line 12 already has the reduced voltage in the dual power scheme, the further instantaneous voltage drop may cause SRAM cell celln-1 to lose the bit value stored in, particularly if the bit value of SRAM cell celln-1 was previously weak. The same problem exists even in the single power scheme when the operation voltage goes into sub-1V territory.
Therefore, new SRAM arrays having improved read and write margins while at the same time overcoming the deficiency of the prior art are needed.